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TEXNET.004
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1988-12-17
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[ Note: This series of articles was found on Compuserve and downloaded
from HAMNET there on 21 July 1985 by Dwight Ernest KA2CNN 70210,523. ]
An Introduction to Networks
part 4
by T.C. McDermott, N5EG
networks SIG, TPRS
This article describes some requirements for network node hardware.
One of the key concepts is the idea of modular implementation - to allow
for changes in the way a network is designed.
The network that has been evolving from the description in the 3
previous articles can be implemented in a backbone type of network. In
this network there are two channels that are accesible at any node, the
high-speed inter-node communication channel, and the 2-meter AX.25
channel. Thus the description of the hardware assumes that there are
two synchronous channels per node.
Each node has the capability to move traffic along between nodes
(all on the high-speed channel) and also to drop and add traffic to the
high-speed channel from the low-speed channel. One of the first
assumptions is that the high-speed channel will operate at 9600
bits-per-sec (b/s). For a number of reasons (the formost of which is
availability) the K9NG type of FSK modem on the 220 Mhz. band will be
utilized. There are some performance advantages to be obtained with
PSK, but the slow carrier-recovery loops that are normally used are not
always compatible with the fast T/R-switching times needed in packet
service. The low-speed channel will compatible with AX.25 TNC's, and
thus is a 1200 b/s channel on the two meter band.
We have thus partitioned the node into three major elements:
1. High-speed channel hardware.
This includes 220 MHZ. radio, antennas, power splitter,
9600 b/s FSK modem (K9NG).
2. Low-speed channel hardware.
This includes 2-M radio, antenna, and 1200 b/s AFSK
modem.
3. Node-control computer.
This includes 2 synchronous interfaces, T/R control
circuits, RAM, ROM, and fail-safe sequence decoder.
A simplification of the high-speed radio circuitry is to have only
one 220 Mhz. transmitter and one 220 Mhz. receiver per node. Two
high-gain directional antennas are used, with a 3-dB. power splitter
near the antennas. Thus communications with the northerly- and
southerly- nodes is possible with one radio. Extension of this concept
to three or four nodes is possible but the RF losses start to get high.
The design of the high-speed portion (the backbone) allows access to the
node only by other nodes. This is done to eliminate direct channel
contention between users and the inter-node communication. The users of
the network do not, and indeed CANNOT communicate with it on 220 Mhz.
The protocol on 220 Mhz. (in this implementation) is TEXNET-IP, which
IS NOT compatible with AX.25 (and indeed, for the reasons expressed in
parts 1-3, should not be compatible with AX.25).
The 2-Meter section can use a commercially-available FM radio, and
AFSK modem design.
Each of the radio sections contains logic-level interfaces to the
node control unit. This is done to facilitate the changeout of the node
control processor should a new design or network protocol standard
become available. It is anticipated that resolution of the various
trade-offs involved in the implementation of a network will take several
years to occur. In order to solve a pressing need within TPRS, the need
for long- haul communication, we will go ahead and implement TEXNET with
an eye towards changes and evolving standards.
The node control computer consists of a Z80-SIO chip (which has two
synchronous HDLC-type serial channels), a Z80 (4 Mhz.) microprocessor,
16K of ROM, 32K or RAM, some timer circuitry to develop the 1200-hz,
9600-hz, and 1200 x 32 = 38400 hz. clocks. The node also has two
time-out timers to prevent transmitter lock-up on the 2-m and 220 Mhz.
units, contains NRZ/NRZI coder, decoder, and clock-recovery circuits for
the 1200 b/s channel. It also contains a special state machine that
listens to the 220 Mhz. channel and clock. This circuit recognizes a
special sequence (that obeys the HDLC coding rules) and interprets the
reception of this sequence as a over-riding command that uses hardware
to re-boot the node processor. Each node contains a unique code in its
state machine. The code is chosen to be sufficiently long that the mean
time to false is 6*10^7 years (assuming random data).
A custom circuit board will be constructed to contain this
controller. It may have been possible to modify one of the Xerox-820
boards, but it was felt that the changes required would reduce the
reliability of the resultant assembly too much. The parts cost of
byte-wide RAMs and ROMs has dropped recently, and these devices will
should allow construction of the entire controller for slightly less
than the price of just the 820 board when purchased surplus.
The controller will be constructed mostly of CMOS circuitry, and
will be powered at +5 V through a series regulator powered from +12 VDC.
This will allow a single +12 V supply. The node will contain a gel-cel
battery and a charger circuit. Thus the entire node will have something
approaching un-interruptable power, while still having an acceptable
power supply cost.
The node controller card will be connecterized at the logic- level
interfaces to the radio circuits. In the event a new controller design
emerges, then upgrading of the node can be as simple as replacing the
card.
One of the objectives of this network design is to keep the cost of
any node low. Our goal was $500.00. We anticipate that those groups
who wish to joint TEXNET will assemble, place, and maintain their node,
with the assitance of TPRS. We thus would release the design of the node
to those groups, and perhaps sell or supply the circuit boards needed,
as well as the software for the controller. In our design, each node
will have the same software, except for routing tables. A first crack
at the routing problem can be attempted with static routing tables,
whcih will be in ROM, and different at every site.
The subjects of routing, and other network topics will be discussed
in part 5 of this series.